As technology nodes shrink, more defects are found in the scan chains that are added to a device for the purpose of test. This is due to a number of reasons, as described in this document. To bring new integrated circuits to market, and to ramp yield to acceptable levels, new methods and apparatus are needed to identify scan chain defects.
Scan chains are critical items for test and yield-bring-up. When they break, they both relegate a device (e.g., a chip) under test to the fail bin (adding to the yield loss problem) and they mask and prevent timely and accurate evaluation of other fails sourcing from combinational, sequential, power-distribution or clock logic.
The approach of design for test (DFT) or scan methodology is to replace all flip-flops in a design with scan flip-flops. Scan flip-flops (or scan cells) provide two paths into each flip-flop: one path for the mission of the design, and a second path to facilitate test.
The two most common approaches to scan flip-flops are the MUXD and LSSD approaches. The MUXE approach places a multiplexer (mux) on the front end of the D-input of a flip-flop. The selector to the mux, known as the scan enable, determines whether to use the mission mode input or the scan test input of the mux. The LSSD approach uses multiple non-overlapping clocks: one pair of which operates separated Master and Slave latches for propagating mission data; and the other pair of which operates the separated Master and Slave latches to produce a scan shift operation. With the LLSD approach, the total scan shift and sample operation may be conducted with just one pair of clocks or with a combination of all of the clocks.
By stitching the scan flip-flops (or scan cells) of a DUT into one or more shift registers called scan chains, each flip-flop can be preset or observed. This allows for test patterns to be constructed that will concentrate on finding faults in sub-circuits of the DUT.
Further descriptive commentary will focus on the MUXD type scan, since it is easier and simpler to describe. In a MUXE type scan, each scan flip-flop has two input paths, controlled by a mux at the flip-flop's D-input. When the scan enable is asserted, the scan chain operates as a shift register. This allows for each flip-flop to be set to a specific state. It also allows for the observation of each flip-flop state as the values are shifted out of the device onto the scan output. Level Sensitive Scan Design is disclosed by Storey et al., “Delay Test Simulation”, 14th Design Automation Conference Proceedings, pp. 492-494 (June 1977), and in U.S. Pat. Nos. 3,783,254 and 4,293,919.
There are several generally accepted models for defects (or faults) in scan chains: blocked chains, bridging, and hold time.
Blocked Chains—This condition is determined by observing the scan outputs while in scan mode. If the output is at a fixed level regardless of the data shifted into the chain, the chain is blocked at one or more points, and the block nearest to the scan output dominates what is observed from that chain. The fault model is generally that the output of the scan chain is either stuck-at-0 or stuck-at-1 from the sequential element located at the point of the block.
Bridging—Bridging faults are a condition of data dependency when data passing through one scan chain can modify data in another scan chain or in a different location in the same scan chain. The suspected mechanism is an “aggressor-victim” short or bridge that is exercised when the two signals involved are at opposite values.
Hold Time—Hold time faults are a condition that allows the data from one flip-flop to race forward in the chain. Hold time faults are attributed to a number of factors, including long wire routes as compared to Clock-to-Q times of flip-flops and clock skew. This condition is suspected when data produced on the output is still toggling but seems skewed (correct response but shifted in time) or when bits are missing (data smearing or bit skipping). Overall, hold time faults can be viewed as “accidental encryption”. If the number of bits applied at the scan input does not match the data on the scan output, it is likely that a hold time fault exists. In some cases, hold time faults make the scan chain appear to have fewer flip-flops than it actually has.
Hold time is a data communication fault between two adjacent cells in a scan chain, where the bit closest to the scan input is the aggressor cell and the bit closest to the scan output is the victim cell. When a hold time fault exists, the victim cell's data value is replaced with the aggressor cell's data value. The resultant data stream shows the aggressor's data twice, and the victim's data is lost. There are three common types of hold time fault.
Standard hold time fault—When both data states (aggressor and victim) are improperly communicated, a fail signature results that simulates a missing flip-flop in the scan chain.
Data One hold time fault—When the aggressor cell's data is a logic one, its data is pulled forward one location, overwriting the victim's data. The resultant fail signature has too many ones.
Data Zero hold time fault—When the aggressor cell's data is a zero, its data is pulled forward one location, overwriting the victim's data. The resultant fail signature has too many zeros.
Typically, to insure that the scan chain test logic is operational, tests will be performed on the scan chain test logic prior to performing tests of a device's functional logic. These tests on the scan chain test logic are commonly known as Scan Chain Integrity Tests. The most common approach is to send a series of 1's and 0's at the scan inputs. With the scan enable asserted, the scan chain is essentially a big shift register. With the continued assertion of the scan enable, the functional logic is removed from the test. After ‘n’ number of clock cycles, where ‘n’ equals the number of scan cells in the chain, the input stream should be observed on the scan output if the scan chain operates correctly.
If the scan chain does not transfer data from a scan input to a scan output reliably, the entire scan methodology is lost. Input data to load the chain and output data to unload the chain are both disrupted. This typically manifests itself as a scan chain integrity failure. This makes the scan chain appear to be shorter than it actually is by at least one flop. The clock skew issue can be caused by design issues such as timing closure, or manufacturing defects such as faulty vias or weak clock-tree buffers. In nanometer geometries, it is often caused by a combination of the two, causing a yield loss due to hold time issues.
Conventional chain integrity patterns produced by ATPG tools today are implemented as a replicated stream of a ‘0-0-1-1-0-0-1-1’ sequence. This sequence has data changing on every other vector. Therefore, a device with a standard hold time fault appears to be shifted by one bit, and the last bit is indeterminate. The last bit that is shifted out is not part of the pattern; it is the state that was on the scan in pin when the scan out sequence was applied. See FIG. 1. Note that the fail signature with a single standard hold time fault is basically pass-fail-pass-fail.
Often, hold time faults are timing sensitive. That is, since the rise time and fall time of a flip-flop's Q output are not symmetrical, a hold time fault may result in an ability of the flip-flop to transfer one data state but not the other. This failure could be caused by the Q-output having a slower rise time than fall time.
The example shown in FIG. 2 assumes a single hold time fault, with “0” being the aggressor state and “1” being the victim state. When devices have multiple hold time faults on a single chain, the data shifts one cycle for each fault. It is quite common for smaller geometry devices to have multiple hold time faults on a single chain. With the standard 00110011 pattern, it is possible for a chain to shift the data 4 positions, and at the end of the pattern actually be passing the scan chain test.
As previously mentioned, in design for test methodology, flip-flops have a dual functionality. During normal or functional mode, they latch data states in the circuit and store values to be transmitted to the next cloud of logic in the design. During test mode, they are used to provide test stimuli to the combinational logic, and to capture the results of the logic operation. To transfer test patterns into and out of a device under test, the flip-flops are reconfigured as one or more serial shift registers.
A type of design problem known as a setup violation can occur if the amount of logic between two banks of registers is so great that the data does not propagate through the logic and become stable at the input to a flip-flop within the setup time allowed before a scan chain is clocked. When this occurs, the result that is clocked into a flip-flop may be invalid. This is solved by design methodologies and tools associated with the term “timing analysis”.
After a desired scan pattern is loaded into one or more scan chains, scan enable is not asserted and the logic of a device is clocked one or more times in mission mode. The result of the logic operation is captured in the device's scan flip-flops. It is desirable to bring this result out of the device under test so that it can be examined by a test system. This is done by putting flip-flops back into serial shift mode, and then applying enough clocks to shift every bit in a number of scan chain(s) out of the scan out port(s). Most designs have some scan chains that are longer than others, so it is important to shift the data enough times for even the longest scan chain to be fully unloaded. Shorter chains are over shifted and therefore get padded with X (don't care) states. This same technique is applied when data is shifted in, where shorter chains are typically pre-padded with dummy “0” data before the actual data stream. At this time, it is common to shift a new test pattern in through the scan in port.
In conventional implementations of scan registers, charge flow or current is required to establish a clock event as well as a state change. A defect in the conductive medium of a device may lower the rate of current so that a state change or clock event may be delayed from its desired time. Furthermore clock signals must be distributed throughout a chip and require buffers to boost current. Any two clock signals may have a difference in arrival at their register, which is called clock skew, and which can be managed by adjusting the buffer size and the routing of the wires carrying the clock signal.
As an example of the effect of a hold time fault, consider a scan chain of length 8 (i.e., 8 bit positions, flip-flops or scan cells), with bit zero (0) closest to the scan out port and bit seven (7) closest to the scan in port. After a functional clock, the state of a device's logic is entirely captured within the scan chain's eight registers, as follows:
V(0) V(1) V(2) V(3) V(4) V(5) V(6) V(7)
In a correct shift register, each of the eight bits is serially shifted out, and a new test pattern beginning with I(0) is shifted in. But, imagine that bit six (6) exhibits a hold time fault. On the first shift clock, V(0) is emitted from the scan out port. However, the fault at bit six (6) causes it to capture V(7) rather than V(6) during this first shift. After eight shift clocks have been applied, the pattern captured at the scan out will be:
V(0) V(1) V(2) V(3) V(4) V(5) V(7) I(0)
Also, consider the above scan chain's corruption of an input test pattern, which might appear as:
I(0) I(1) I(2) I(3) I(4) I(5) I(7) I(N)
It may be appreciated that scan chains may be conventionally comprised of 10,000 registers (i.e., flip-flops or cells), and that even if less than 1 percent exhibit a hold time fault, hundreds of bits in a scan chain may be invalidated.
It is noted that, in the following description, like reference numbers appearing in different drawing figures refer to like elements/features. Often, therefore, like elements/features that appear in different drawing figures will not be described in detail with respect to each of the drawing figures.